Homework 1

All designs and simulations must be done at 0.5 micron design.
 
• Design and layout a CMOS NAND gate and a CMOS transmission gate; simulate its working using Spectre. Submit your results using the instructions for submission (link will be available before due)

• Design a 4 bit full adder in schematics.  Show the simulations using spectre.

    Due Thursday 9/25/2003 12:00 midnight.  Late submissions will be accepted at 10% penalty till 9/26/2003 12:00 midnight.