High Performance VLSI Systems and Architecture Laboratory

Department of Computer Science and Engineering

 

Director: Ramalingam Sridhar   Office: 135 Bell Hall, Lab location: 2 Baldy Hall

 

Research Focus: VLSI Circuits and Systems, Embedded Technologies, Wireless Networks and Security, Computer Architecture

 

Members  

Funding Source

Publications   

Patents 

 

Research Projects:

 

·        VLSI Systems and Architecture: Memory Systems research overview:

Ø  Leakage reduction for SRAM Arrays (bit level and block level): Subthreshold leakage reduction (NC-SRAM) (3), Gate Leakage reduction in SRAMs (4,5), Robust Sense amplifiers (WTA, LPCSA) (6,7), System level approach to leakage reduction and variation tolerance, by applying leakage and variation models to CACTI (2, 1),  SRAM stability, Variation tolerance and litho-aware design, memory sub-systems with increased Read and Write Stability for sub-65nm designs

References:

1.     M. Agarwal, L. Liu, P. Elakkumanan and R. Sridhar, “Intra-Die Process Parameter Variation and Leakage Analysis of Cache at the Microarchitectural Level”, IEEE SoCC (System on Chip Conference), Hsinchu, Taiwan, September 2007

2.     L. Liu, M. Agarwal, P. Elakkumanan and R. Sridhar, “CacheLeakage: A Leakage Aware Cache Simulator”, 50th Midwest Symposium on Circuits and Systems, Montreal, Canada, August 2007

3.     P. Elakkumanan Elakkumanan, A. Narasimhan and R. Sridhar, "NC-SRAM - A Low-Leakage Memory Circuit for Ultra-Deep Submicron Designs",  Proceedings, IEEE International SoC Conference 2003, Portland, OR, September 2003, pp. 3-6

4.     C. Thondapu, P. Elakkumanan, R. Sridhar, “RG-SRAM: A Low Gate Leakage Memory Design for Sub-70nm Process”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), May 11-12, 2005, Tampa, FL, pp. 295-296

5.     P. Elakkumanan, C. Thondapu and R. Sridhar, “DG-SRAM: A Low Leakage Memory Circuit”, IEEE System on Chip Conference, Washington, D.C., September 25-28, 2005, pp. 167-170

6.     S. Sundaram, P. Elakkumanan and R. Sridhar, “High Speed Robust Current Sense Amplifier for Nanoscale Memories -- A Winner Take All approach”, 19th International Conference on VLSI Design, January 2006, pp. 569-574.

7.     S. Sundaram, P. Elakkumanan and R. Sridhar, “LPCSA: A Novel Low Power Current Sense Amplifier for Nanoscale SRAMs”, Austin Conference on Integrated Systems & Circuits, Austin, TX, May 17-19, 2006

8.     L Liu, M. Agarwal, P. Elakkumanan and R. Sridhar, “CacheSim: A Cache Memory Simulator with Intra-Die Process Parameter Variation and Leakage Models”, Austin Conference on Energy-Efficient Design (ACEED), 2007

9.     P. Elakkumanan, L. Liu, V. Vankadara and R. Sridhar, “CHIDDAM: A Data Mining based Technique for Overcoming the Memory Bottleneck Problem in Commercial Applications”, 48th IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, OH, August 7-10, 2005, pp. 1888-189

10.  M. Agarwal, R. Sridhar, “Analysis, design and fabrication of SRAM memory sub-systems with increased Read and Write Stability for 65nm technologies and beyond”, Univesity at Buffalo, CSE Technical report 2008.

11.  L. Liu, P. Nagaraj, S. Upadhyaya and R. Sridhar, “Defect Analysis and Defect Tolerant Design of Multi-port SRAMs”, Journal of Electronic Testing, Springer, 2007

·        Interconnects, clocking, synchronization:

References

1.      R. Sridhar: System-on-Chip (SoC): Clocking and Synchronization Issues. Invited Paper, VLSI Design 2004: 520-527

2.      A. Narasimhan and R. Sridhar, “Impact of Variability on Clock Skew in H-tree Clock Networks”, International Symposium on Quality Electronic Design (ISQED), March 26-28, 2007, San Jose, CA

3.      A. Narasimhan, Y. Nahvi and R. Sridhar, “Variability Tolerant Reliable Clock Distribution Networks”, Austin Conference on Energy-Efficient Design (ACEED), 2007

4.      A. Narasimhan, B. Srinivasaraghavan  and R. Sridhar, “A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects”, 19th International Conference on VLSI Design, January 2006, pp.491-494.

5.      A. Narasimhan, K. Srinivasan and R. Sridhar, “A High-Performance Router Design for VDSM NoCs”, IEEE System on Chip Conference, Washington, D.C., September 25-28, 2005, pp. 301-304

6.      A. Narasimhan, G. Kumaravelu, R. Sridhar, “An Investigation of the Impact of Network Parameters on Performance of Network-on-Chips”, 48th IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, OH, August 7-10, 2005, pp. 1617-1620

7.      A. Narasimhan, M. Kasotiya and R. Sridhar, “A Low-swing Differential Signaling Scheme for On-Chip Interconnects”, Proceedings, 18th International Conference on VLSI Design, 2005, pp. 634-639

8.      A. Narasimhan, S. Divekar, P. Elakkumanan and R. Sridhar, "A Low-power Current-mode Clock Distribution Scheme for Multi-GHz NoC-based SoCs", Proceedings, 18th International Conference on VLSI Design, 2005, 130-133

9.      Kim and R. Sridhar, "Buffered Single-Phase Clocked Logic for High-speed CMOS pipelined circuits", IEEE International Symposium on Circuits and Systems  `97, June 1997, Hong Kong

10.   Kim and R. Sridhar, "Hierarchical Synchronization Scheme Using Self-timed Mesochronous Interconnections", IEEE International Symposium on Circuits and Systems  `97, June 1997, Hong Kong

·         High Performance Circuits, CMOS Wave-pipelining, Asynchronous Circuits:

·        Soft Errors, Very deep submicron VLSI Circuits and Systems:

References

1.      M. Agarwal, P. Elakkumanan and R. Sridhar, “Leakage Reduction for Domino Circuits in sub-65nm Technologies”, IEEE System on Chip Conference (SoCC 06), Austin, TX, September 2006

2.      P. Elakkumanan, K. Prasad, and R. Sridhar, “Time Redundancy Based Scan Flip-Flop Reuse to Reduce SER of Combinational Logic”, International Symposium on Quality Electronic Design (ISQED), March 27-29, 2006, San Jose, CA, pp. 617-624.

3.      P. Elakkumanan, K. Prasad, and R. Sridhar, “Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits”, Journal of Low Power Electronics, American Scientific Publishers, August 2005, vol. 1, No. 2, pp. 182-193

4.      P. Elakkumanan, V. Anathakrishnan, A Narasimhan and R Sridhar, "Leakage Aware SER Reduction Technique for UDSM Logic Circuits", Proceedings, IEEE International SoC Conference 2004, September 2004, pp. 82-85

 

·        Architecture, applications, SoCs:

 

·        Wireless Networks and Systems Cross Layer techniques to Energy reduction in wireless ad hoc networks, ad hoc wireless network header compression, Wireless security, Wireless network authentication protocol, Cryptosystems for Wireless Ad Hoc Networks, Sensor Networks design, Energy in sensor networks, Security in Sensor networks, RFID, Smart Cards integration, Energy - performance - security tradeoffs, embedded secure architectures

  Research Group

Current Members

Ph.D. Graduates 

M.S. Graduates (Thesis)  

Other researchers

 

Current Students:

 

·        Kerry D. Courtright, Ph.D. candidate, "Tamper resistance and IP protection in embedded applications"

·        Ashok Narasimhan, Ph.D. candidate, "Clocking and Synchronization issues in Very Deep Submicron System"

·        Lushan Liu, Ph.D. candidate, "Reliable Memory Architectures and Low Power SRAMs in SoCs"

·        Geethapriya Thamilarasu, Ph.D. student, "Cross-layer Approach to Intrusion Detection in Wireless and Sensor Networks"

·       Manjari Agarwal, "Very Deep submicron VLSI Noise issues”, Started January 2005

·       Sriram Sankaran, “Energy efficient security approach to sensor networks”

·       Santhosh Kumar Reddy, “Globally Asynchronous Locally Synchronous approach for reliable deep submicron SoCs”

 

Ph.D. Graduates:

 

Praveen Elakkumanan, Ph.D. September 2006, Dissertation: “Overcoming the Circuit Design Challenges in Nanoscale SRAMs”; MS Thesis “Low Leakage High Performance Static Random Access Memories”, Aug 2003– IBM Semiconductor Research and Development Center, NY

 

Kris Schindler, Ph.D.February 2002, Thesis: "Energy Efficient Design Methodology for Combinational Logic Circuits" - University at Buffalo, CSE Department


Alfonso Martinez-Smith, Ph.D.  2000, Dissertation: "Framework and Methodology for Object-Based Hybrid Visual Processor Architecture Design" - Mutimedia Research Lab, Motorola Corporation, Schaumbug, IL

 

Wen-Jann Yang , Ph.D., SUNY at Buffalo, September 1998, Dissertation: "Access Schemes for Multi-Attribute-Cecord Ctructure and Color-content based Image Retrieval" - Telecom Technology Services, Pleasonton, CA

 

Dipankar Talukdar, M.S. SUNY at Buffalo, 1993 Thesis: "An Adaptive Thresholding Technique and its ASIC implementation"; Ph.D. SUNY at Buffalo, June 1997, Dissertation: "Issues in the Design of Pipelined VLSI Circuits for DSP Applications" – Tzero Technologies, Sunnyvale, CA

 

Sanu Mathew,  M.S. September 1997, Thesis: "Efficient Clocking of Wave-Domino Pipelined Systems"; Ph.D. September 1999, Dissertation: "Data-driven Self-timed logic systems" - Intel Microprocessor research lab,  Hillsboro, OR

 

Seokjin Kim,  M.S. 1993. Ph.D. 1997, Dissertation: "Hierarchical Synchronization Scheme for Structured VLSI Systems, AMD, Boston, MA

 

Yong-Chul Shin, M.S. 1990, Thesis: "A General Purpose Parsing Processor for LALR Class of Languages";  Ph.D. 1994, Dissertation: "Non-Fully Configured Second-Order Neural Networks using Multi-Dimensional Weights" - CTO, Cedar Tech, Williamsville, NY


MS Graduates (Thesis)

 

Yawar M. Nahvi, M.S. February 2007, “Transmission-Gate based Variation Tolerant Active Clock Deskewing for Deep Submicron System on Chips (SoCs)”

 

Manjari Agarwal, M.S. August 2006, Thesis: “Charge-Sharing and Leakage Reduction in Domino CMOS Circuits”, - Continuing Ph.D.

 

Karthik Ramakrishnan, M.S. August 2006, Thesis: “Wireless Network Security using a Low cost Pseudo Random Number Generator”, - Morgan Stanley, New York, NY

 

Kishan Prasad, M.S. August 2005, Thesis: “Circuit Level Techniques for Reducing Radiation Induced Soft Error Rate (SER) in Nanoscale Combinational Circuits”

 

Aruna Balasubramanian, M.S. February 2005, “A Hybrid Security Solution for Mobile Ad Hoc Networks”, University of Massachusetts, Amherst, MA

 

Ghuru Kumaravelu, M.S. February 2005, “Virtual Cut ThroughSwitching for Network on Chip Architectures”. Pactron/HJPC, Sunnyvale, CA

 

Vijaykumar Vankadara, M.S. September 2004, “Cache Hierarchy Design for Memory Intensive Applications”, Canto, San Francisco, CA

 

Camil Fayad, M.S. February 2004, Thesis: “Montgomery Modular Arithmetic  Implementation in Crypto Engines for System on Chip (SOC) Design” - IBM Corporation, Poughkeepsie, NY

 

Roopa Raghunathan, M.S. September 2003, Thesis: "Power Reduction through Effective Slack Timing Utilization" – Magma Design Automation, Santa Clara, California

 

Ranjani Sridharan , M.S. September 2003, Thesis: "Reconfigurable Opcodes Instruction Set Architecture for Software Security" - Ph.D. at Texas A&M, College Station, TX


Srivathsan Krishnamohan, M.S. September 2003, Thesis: "Orthoganal Instruction Set Architecture for Network Capable Applicaiton Processor" - Ph.D. student Michigan State University, East Lansing, MI

 

Divya Chandrasekharan, M.S. September 2003, Thesis: "Accurate Power Estimation at Register Transfer Level with Leakage Consideration", - Mediatech, Virginia

Hanseu Park, M. .S. 2001, Thesis: "Impact of Deep Sub Micron on Technology on Wave-pipelining” - IBM Corporation


Veena Pureswaran, M. .S. 2001, Thesis: "Reconfigurable DSP template for Multimedia processors” - IBM Corporation, North Carolina

 

Anand Lakshmanan, M.S. May 2001, Thesis: "Noise tolerant dynamic circuit” - Intel Corporation

 

Subramanian Sankaran, M.S. February 2000, Thesis: "Crosstalk analysis and clustered voltage scaling techniques in CMOS Designs" – Qualcomm, San Diego

 

Venkatesh Doraiswamy, M.S. February 2000, Thesis: "Impact of Interconnects on Deep submicron Wave-Pipeline designs" - Intel Corporation, Santa Clara, CA

 

Shu Xia, M.S.- “Foveal Vision System Design and characterization”, February 1999. Teradyne Corporation, Boston, MA

 

Shahar Dor, M.S. February 1998, Thesis: "On-line Delay-Fault Detection and Correction of Reliable Wave-Pipelining" -  Sun Microsystems - Austin, Texas

 

Jay Anderson,  M.S. August 1998, Thesis: "A New Circuit State Retention Scheme for Multi-threshold Voltage CMOS Circuits" - Ph.D. Carnegie Mellon University, Pittsburgh, PA


Hemil B. Patel, M.S. September 1998, Thesis: "Supply-Threshold Voltage Scaling for Speed-Power Trade-Off" - LSI Logic


Daniel R. Pilhorn,  M.S. September 1998, Thesis: "Issues in the Power Analysis of Digital Signal Processors" - Lockheed Martin Federal Systems Division

 

Paul DeMarco, M.S. September 1998, Thesis: "Issues in the Design of a DSP FPGA Architecture" - Lockheed Martin Federal Systems Division

 

Guhan Krishnan, M.S. September 1998, Thesis: "Partial Binding specifications for low power High Level Synthesis" – AMD, Boston, MA

 

Rajesh S. Parthasarathy, M.S. August 1997, Thesis: "Design of Wave pipelined Arithmetic Units using Double Pass Transistor Logic" - Intel Corporation, Hillsboro, Oregon

 

Mathew Greenberg, M.S., August 1997, Thesis: "A Hardware Implementation of a Two Dimensional Discrete Cosine Transform" - Applied Signal Technology, Sunnyvale, California

 

Brian McGee,  M.S. 1995, Thesis: "Low Power Issues in Wave Pipelined Systems" -Sun Microsystems, California

 

Enrique Fernadez Herrera, M.S. 1995, "Dual Rail Static CMOS Architecture for Wave Pipelining" - Universidad Centroamericana Jose Simeon Canas, El Salvador

 

Ramkumar Krishnamurthy, M.S. 1994, Thesis: "Wave-pipelined CMOS Implementation of Morphological Processors"; Ph.D. Carnegie Mellon University, Pittsburgh, PA.-  Intel Microprocessor Research Lab

 

Xuguang Zhang, M.S. 1994 - PairGain Technologies Inc., Tustin, California

 

Frank K. Li, M.S. 1993, Thesis: "Practical Asynchronous Design Techniques and Analysis"

 

Sanjay Fotedar, M.S. 1993. Thesis: "Underline Detection and Removal System using Hough Transform" - NCR Corporation


Chandra S. Bharathi, M.S. 1993, Thesis: "Data Structures and Compression Techniques for a Large Read-only Memory resident database", - Intersolv.

 

Parag Gokhale, M.S. 1992. Thesis: "System Controller and System Integration for the Real-time Address Block Location System" - Accurate Corporation, New Jersey.


Douglas Hall, M.S. 1992. Thesis: "A Processor for Symbolic and Numeric Applications.

 

Rajesh Dixit, M.S. 1992, Thesis: "Handwriting/Machine Print Discrimination and Character Recognition in Address Block Location System" - Jones Inc, Texas.

 

Sudeep Narain, M.S. 1991, Thesis: "Design and Simulation of an Architectural Framework for an Intelligent Decision Support System".


Dirk Naumann, M.S. 1991, Thesis: "Design and Implementation of a Self-timed Microprocessor"

 

Vassilios Axaris, M.S. 1990, Thesis: "An Architecture for a Prolog Coprocessor". Emporiki Bank - Cyprus Ltd, Information Technology and Operations Division, Cyprus

 

Martin Gilbert, M.S. 1990.  Thesis: "Design Techniques for the realization of an Asynchronous RISC and Microcontroller - NASA Jet Propulsion Laboratory

 

Other Researchers

 

 Hua-Feng Chen, M.S. 1995, Broadcom, Arizona

 

Vidya Bharrgavi Balasubramanyn, MS (Project) 2007; Topic: Biosensor networks security


Srikanth Sundaram, M.S. 2006. Research Topic: Sense Amplifiers – Texas Instruments, Texas

 

Charan Thondapu, M.S. 2005. Research Topic: SRAM Leakage control – Broadcom, California

Karthik Srinivasan, M.S. 2005. Research Topic: SRAM Leakage control – Apache Design Solutions, Mountain View, California

Bhooma Srinivasaraghavan, M.S. 2006. Research Topic: Drivers for Interconnects

 

Manish Kasotiya, M.S. 2005 Research Topic: Signaling for On-chip interconnects

 

Shantanu Divekar, M.S. 2005, Research Topic: Low power Clock distribution through current mode signaling

 

Viswanathan Natarajan, Research Topic: Security in RFID based Wireless networks

 

Viswanathan Ananthakrishnan. M.S. 2004, Research Topic: Soft Error and Leakage Control

 

Brian Bart, M.Eng. 1996. Project Title: “Foveal Vision sensor prototype design” - Intel Corporation, Folsom, California

Funding:

Microelectronic Design Center (MDC) supported by NYSTAR

 

National Science Foundation

 

NASA, Air Force, Amherst Systems.

 

Publication:

2007

G. Thamilarasu and R. Sridhar, “Toward Building a Multi-level Robust Intrusion Detection Architecture for Distributed Mobile Networks”, Fifth Inernational Workshop on Mobile Distributed Computing (MDC 07) in conjunction with International Conference on Distributed Computing Systems (ICDCS), Toronto, June 29, 2007

V. Bharrgavi Balasubramanyn, G. Thamilarasu and R. Sridhar, “Security Solution For Data Integrity In Wireless BioSensor Networks”, First International Workshop on Specialized Ad Hoc Networks and Systems (SAHNS 2007) in conjunction with International Conference on Distributed Computing Systems (ICDCS), Toronto, June 29, 2007

A. Narasimhan and R. Sridhar, “Impact of Variability on Clock Skew in H-tree Clock Networks”, International Symposium on Quality Electronic Design (ISQED), March 26-28, 2007, San Jose, CA

L Liu, M. Agarwal, P. Elakkumanan and R. Sridhar, “CacheSim: A Cache Memory Simulator with Intra-Die Process Parameter Variation and Leakage Models”, Austin Conference on Energy-Efficient Design (ACEED), 2007

A. Narasimhan, Y. Nahvi and R. Sridhar, “Variability Tolerant Reliable Clock Distribution Networks”, Austin Conference on Energy-Efficient Design