ContactPerson: ks87@cse.buffalo.edu
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### Begin Citation ### Do not delete this line ###
%R 2004-07
%U /tmp/DFM.ps
%A Karthik Sundararaman
%T Design For Manufacturability - Fault Model Extensions for RF Circuits with
an Economic Perspective for Manufacturability
%D May 18, 2004
%I Department of Computer Science and Engineering, SUNY Buffalo
%K LNA, Cost Modeling, Fault Models, DFT, Reliability
%Y Economics; Reliability; VLSI Testing
%X Design For Manufacturability issues have started escalating the problem of Design and Test in the Deep Submicron era. Two questions posed are
"How good is the quality?" and "How expensive is the product?" To ensure quality one needs to answer the question "To DFT or Not to DFT." New Analog
and RF designs lack good DFT techniques due to inadequate fault models. Using existing test techniques that are largely outdated, one has to and 
out if the solutions are economically feasible for the vendor to implement in his designs. The quality issues of RF cores and the economic issues
of mixed signal cores and standalone chipsets are addressed in this thesis from a DFM standpoint. A lot of emphasis has been placed on the test cost
of chips and a variety of models have been proposed in the literature. Existing models are incomplete with the fact that most do not take into account
the costs involved once the chip reaches the market. This thesis focuses on the cost economics of fault tolerant chips and how RF cores fit into the
whole economic model for new designs. New fault models which could help improve the testability of circuits (hence improving quality) are discussed
here. The focus is then moved to an economic cycle where mathematical estimates of the costs for new designs are given. This model will help designers
analyze the need for a fault tolerant system and its feasibility in the industry using the reliability of the system. It will help evaluate the costs
involved during the life cycle of a chip. Design tools - SpectreRF and ASITIC have been used for modeling RF circuits at 0.25u technology. Carafe tool
has been used to perform fault analysis on the layout of the circuit to model realistic faults. Existing fault models for resistors and capacitors
have been verified and a new fault model for inductors has been proposed using these tools. The fault models will help improve the design of RF
circuits by enforcing more constraints on design specific issues. The cost models proposed in this thesis will help designers identify key areas
of cost and help clamp down unnecessary expenses where possible.