module example1;
    /* gate level model to implement the cicuit */
   wire a, b, c;

   wire f;

   submod ckt1(f, a, b, c);

   submodTester st(a,b,c, f);
   
   
endmodule




module submod(f, a,b,c);  
   output f;
   
    input a, b, c;
    
   
    and (t1, a,b),
        (t2, b,c);
    or  (f, t1, t2);
endmodule


module submodTester (a,b,c,f);
    output a,b,c;
    input f;
   
    reg  a,b,c;
    
    
    initial begin
       $monitor ("A: %d  B: %d C: %d  f: %d", a, b, c, f);

       a= 1'b0; b = 1'b0; c= 1'b0;
       
       #10
	        b= 1'b0; c = 1'b1;
       #10
	        b= 1'b1; c = 1'b0;
       #10
	        b= 1'b1; c = 1'b1;
       #10
	 a= 1'b1; b = 1'b0; c = 1'b0;
       #10
	        b= 1'b0; c = 1'b1;
       #10
	        b= 1'b1; c = 1'b0;
       #10
	        b= 1'b1; c = 1'b1;

#20      
	 
       $finish; 
end endmodule