Lushan Liu received her BS degree in Computer Engineering from Beijing Polytechnic University, Beijing, China, in 2000. She earned her MS in Computer Engineering from the State University of New York at Buffalo in 2003, where she has been a Ph.D. candidate under Prof. Ramalingam Sridhar since 2005. She was a summer intern at Agere Systems as Design Verification Engineer working on Network Attached Storage(NAS) chip in 2005, and she also interned at CompSys Technologies in 2006. Lushan joined Marvell Semiconductor in 2007 as Senior Design Verification Engineer in the Microprocessor group. Her research interests include computer architecture, performances analysis, low power reliable SRAM memory design, testing and modeling, ASIC design and verification.

Publications

Lushan Liu, Pradeep Nagaraj, Shambhu Upadhyaya and Ramalingam Sridhar "Defect Analysis and Fault Tolerant Design for Multi-port SRAMs" Journal of Electronic Testing, July, 2007

Manjari Agarwal, Lushan Liu, Praveen Elakkumanan, Ramalingam Sridhar, "Intra-Die Process Parameter Variation and Leakage Analysis at the Microarchitectural Cache Level", IEEE International SOC Conference (SOCC), 2007, Hsinchu, Taiwan, September, 26^th~29^th, 2007

Lushan Liu, Manjari Agarwal, Ramalingam Sridhar and Praveen Elakkumanan "CacheLeakage: A Memory Leakage Modeling Tool for Very Deep Submicron SoCs", IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2007), Montreal, Canada, August 5^th-8^th, 2007

Lushan Liu, Manjari Agarwal, Praveen Elakkumanan, Ramalingam Sridhar "CacheSim: An Energy and Variation-Aware Cache Modeling Tool", the fifth annual IBM research Austin Conference on Energy-Efficient Design (ACEED 2007), March 5^th, 2007

Lushan Liu, Praveen Elakkumanan, Ramalingam Sridhar "Design Exploration of Memory Structures for Power-Aware High Bandwidth Caches", submitted to IEEE VLSI Design Conference, Jan 6^th  ~ Jan 10^th, 2007, Bangalore, India

Lushan Liu, Ramalingam Sridhar and Shambhu Upadhyaya "A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells", 21^st IEEE VLSI Systems (DFT'06), Oct. 4th-6th, Washington DC, USA

Praveen Elakkumanan, Lushan Liu and Ramalingam Sridhar "CHIDDAM: A Data Mining based Technique for Cache Hierarchy Determination in Commercial Applications", IEEE MWSCAS, Aug, 2005, Cincinnati, OH

Talks

"CacheSim: An Energy and Variation-Aware Cache Modeling Tool", the fifth annual IBM research Austin Conference on Energy-Efficient Design (ACEED 2007), Austin, TX, March 5^th, 2007

"Effect of Process Variation on the Performance of Phase Frequency Detector", 21^st IEEE VLSI Systems (DFT'06), Oct. 6^th, 2006, Washington DC, USA

"A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells", 21^st IEEE VLSI Systems (DFT'06), Oct. 6^th, 2006, Washington DC, USA

"CHIDDAM: A Data Mining based Technique for Cache Hierarchy Determination in Commercial Applications", IEEE MWSCAS, Cincinnati, Aug, 10^th, 2005

"System Level Modeling of NAS (Network Attached Storage) Controller Chip by VaST", Summer Intern Student Presentation Contest, Agere Systems, Allentown, PA, July 25^th, 2005

"Power Aware Memory System Design for Very Deep Submicron (VDSM) SoCs", Ph.D. Dissertation Proposal Defense,  Department of Computer Science and Engineering, State University of New York at Buffalo, June, 16^th, 2005

Last  modified on 06/18/2008