Post Layout Simulation Using SpectreS
After we complete the layout
, we also need to put labels for it (such as for an inverter, we need Vdd!
Gnd In Out as labels). Use Create->Label... or shortcut "l" to put labels
from layout window.
The layout should be extracted and simulated using SpectreS , to verify
its correctness. Please follow the steps below to extract and simulate
a layout:
1) Select Verify->Extract from
the Layout window. Leave the default values for most of the fields
except Switch Names. Click on Set Switches and select Extract_parasitic_caps and Keep_labels_in_extracted_view from the popup window.
This will extract the parasitics
from your layout and display the labels in the extracted view. For a description
of other extraction options
http://www.cadence.ncsu.edu/doc/cdsuser/verification.html.
The extraction window
looks like this:
Check in your CIW window to see if there are any errors. If there are no
errors, you will see
an extracted view in the library manager.
2) Open the extracted view. Once the extracted view is open,
choose Tools->Analog Environment
from the extracted view window. This will open up the Affirma Analog
Circuit Design Environment
Window(This will be called SimW in the rest of the document).
The design name appears
automatically in this window. The simulator needs to be setup by specifying
model path and the kind of
simulation required.
3) From the SimW choose setup->Simualtor/Directory/Host.. This will pop up a window
By default the simulator is set to hspice, change this to spectreS as shown
above. Change the Project
Directory field if you want specify a path different from the one given.
4) The Temperature and Model corner for simulation can be changed
, if the simulation needs to be done at
Worst case or Best case. Choose the Temperature and Model Corner
submenus from the Setup menu
in the SimW, if simulation is to be done for PVT(Process, Voltage
, Temperature) values other
than nom(nominal case).
5) The SpectreS simulator has been setup. Select the type
of Analyses needed by clicking
on Analyses->choose from the SimW.Select the required analyses from the Choosing
Analyses
window. For e.g if you want to do a transient analyses, select the tran
button. Specify the stop
time for the simulation in the Stop Time field. If it 100 nano
secs. it is 100n or 100e-9.
6) We also need to set up the model path for the simulator
/eng/tools/cadence_3/local/models/spectre/nom/
7) The input values need to be specified
to do the simulation. This can be done by editing the
netlist generated from SimW. To create the netlist choose Simulation -> Netlists -> Create Final.
The netlist is displayed in a window once it has been created.The first
line in the netlist tells you
where it has been created. Go to this path to edit the netlist. For e.g
if you are simulating
the layout of an inverter and the simulation directory was chosen as ~/cadence/simulation,
then
the netlist file will be ~/cadence/simulation/INV/spectreS/extracted/netlist/spectreFinal
.
8) Once you have reached the above mentioned path, open the file spectreFinal(the
final netlist to
edit it). In the netlist there will be a line saying when the netlist
was generated like "* Generated on
Sep 16 15:54:03 2003". Add the global power net definitions immediatly after
this line. (There are
two
lines having "Sep 16
15:54:03 2003" Please
copy and paste the following 2 lines
after the first occurance)
* global net definitions.
.GLOBAL vdd\!
9) You need to specify the value of Vdd! with respect to ground. This
can be done by adding the
following line:
v0 (vdd\! gnd) vsource type=dc dc=5.0
This statement creates a source v0 (a voltage source varible) between vdd!
and gnd with a value of
5 volts. Add this line just above the circuit definition part.
In addition, we also need to specify the voltage for gnd node:
v1 (gnd 0) vsource type=dc dc=0.0
10) Specify a input source for all the inputs in your circuit.
The following statements show
you how to add a dc source and a pulse waveform. Suppose the input
node is called In in
your layout , the DC source is specfied as:
v2 (in gnd) vsource type=dc dc=<value of voltage required>.
To specify a pulse waveform:
v2 (in gnd)
vsource type= pulse val0=0.0 val1=5.0 delay=2n rise=5n fall=5n width=10n
period=50n
We can use either
DC source or pulse for the input signal. Here we use pulse signal.
11) The type of analyses has been specified in the simW itself.
If you look at the bottom of the
netlist a statement corresponding to that will appear. The following
is final like for the part
we need to edit. Make sure the node names for transistor
terminals and input controls are matched.
12) Run the simulation by typing the following command at the unix
prompt:
spectre -r ../psf/ -f psfbin -E spectreFinal
check to see if there are no errors produced in the simulation.
The last line of simulation will read like this in case of no errors.
spectre completes with 0 errors, 0 warnings, and 2 notices .
13) Once the simulation completed successfully, the results could be viewed
. Type
awd -dataDir ../psf &
at the unix prompt. This will open up a CIW for the awd, calculator
and a Results Browser.
14) Go to the Results Browser and click on psf and then on timeSweep-tran
. This will display
all the input and Output pins in your design. Left click on the pins
to be plotted.
The selected pin will appear on the calculator. click on plot in the calculator
and the waveform is plotted.
