We need to use shift+f to see the full view of transistors, and then do the routing. Make sure to add the contacts for the bulk of NMOS and PMOS (Bulk of NMOS to gnd, Bulk of PMOS to Vdd) as shown below, otherwise, the bulk terminal of transistor appeared in the netlist won't have the correct connection. For an transistor M1 (source gate drain bulk)





          After we've done with the layout editing, we may want to do the simulation for it to make sure it is work. Regarding layout simulation, we can reference the simulation steps for the inverter .

          Supposed we have a schematic view of an inv already, and we need to work on the layout.




          To find an instance from a library for layout, we can go the "Create->Instance..." in Virtuoso Layout Editing window




          Select a desired library and cell, such as we are selecting the layout of INV from UT_LP_AMI06. We can also select from icfb ( iit cells ) library. In UT_LP_AMI06, the schematic view is also available.




             The inverter instance is selected, and put it in the layout view of a cell inv,




            Use shift+f to see the full view, and then add labels in order to use them to generate pins, we can also generate pins directly. The labels must be added to the current view. Make sure the input and outputs are same as in schematic. Here, for example they are "In", "Out". After the labels are put in, we can use "Create-> Pins from labels..." to add pins. We may also need to select a pin layer. such as metal1.
 


 


                   Finally, when we use the two gates created above to build an "and" gate, we can first come up with the schematic by using the gate symbols.



                            Then we can use Schematics to layout conversion to convert this schematic to layout, since we have got the layout views for both of nand and inv. We can take a look of incomplete nets by "Connectivity-> Show incomplete nets..."




                        The advantage of using this way to generate more complex gate is the connectivities between the gates are also dervied from schematic

                        Finish the connections as indicated, and we can also use extracted view to see the connection.



 
                     Then we may want to follow the steps in inverter simulation page to verify the layout.