CSE 493/593 Fall 2011

Lab Assignments

Note: The submission command submit_cse493 (submit_cse593) works.

Lab 1:

Out approximately on Monday, Sep 12. Due on Monday, Sep 19 (our next lab)

You may want to go over the Cadence Info and Tutorial pages as you work on this assignment. The documentation provided under the Help menu in each Cadence tool also has detailed information on using the tools. You may want to create a new library and name it Lab1 for this assignment.

Design a CMOS inverter in Cadence. The width of the NMOS and PMOS transistors should be 1.5um and 3um, respectively. Their lengths can both be set to 0.6um. For simulations, set the inverter input signal to have a rise time of 0.5ns, fall time of 0.5ns, pulse width of 2ns, period of 5ns.

a.     Create the inverter schematic using Virtuoso Schematic L

b.     Simulate the inverter using Spectre simulator in the Analog Design Environment L tool. Measure the propagation delay of the inverter in the waveform window

c.      Create an inverter symbol using Virtuoso Schematic L

d.     Layout the inverter in Virtuoso Layout XL and obtain the rough layout area.

e.       Extract the layout and simulate it.

Lab 2:

Out approximately on Monday, Sep 19. Due on Monday, Oct. 3

Design the NAND and NOR gates at the schematic, symbol and layout levels. Use transistor sizes and as described in Lab 1. Simulate the gates symbol and layout cells using input waveforms such that all possible input combinations occur during simulation. (input1: pulse width=2ns, period=5ns, input2: pulse width=4ns, period=9ns. rise/fall times=0.5ns)

Lab 3:

Out approximately on Monday, Oct. 3. Due on Monday, Oct 10 (our next lab)

Implement a 4:1 MUX circuit using the following circuit design styles – Static CMOS and Transmission Gate logic. Schematic and layout are both required. Use transistors sizes PMOS: W=3um, NMOS: W=1.5um, lengths L=600nm. Period, pulse width and rise/fall times of input waveforms can be assumed to be same as the values used in the earlier lab assignment.

Lab 4:

Out approximately on Monday, Oct 10. Due on Monday, Oct 17 (our next lab)

Design a 4-bit static CMOS ripple carry adder circuit at the schematic and layout levels. The block diagram of the adder circuit is shown below. First design the 1-bit full adder circuit (both schematic and layout). Then create a schematic symbol and use it in constructing the 4-bit adder schematic. For the 4-bit adder layout, instantiate the 1-bit full adder layout and connect the terminals appropriately. Use transistors sizes PMOS: W=3um, NMOS: W=1.5um, lengths L=600nm.

 Lab 5:

Out approximately on Monday, Oct 17. Due on Monday, Oct 31 )

Transmission gate logic: Implement a full adder circuit in schematic and layout using T-gate logic, and verify them. Measure the delay time and power consumption, and compare it to the result of the CMOS design in last lab. Use transistors sizes PMOS: W=3um, NMOS: W=1.5um, lengths L=600nm.

Lab 6:

Out approximately on Monday, Oct 24 Due on Monday, Oct 31 (our next lab)

This lab is designed to help you understand the relation between timing and size of transistors.

Note: only schematic level simulation is required; you do not need to implement layout design.

Implement a CMOS inverter using transistors sizes PMOS: W=3um, NMOS: W=1.5um, lengths L=600nm. Calculate the rise time and fall time. And then, (1) keep the size of NMOS and change the width of the PMOS to 4um, and calculate the rise time and fall time. Also, (2) keep the size of PMOS and change the width of the NMOS to 3um, and calculate the rise time and fall time again. Please conclude the general rule of sizing and timing.

Lab 7:

Out approximately on Monday, Oct 31 Due on Monday, Nov. 7 (our next lab)

Design a 5-stage Ring Oscillator. Use minimum width and length for the PMOS and NMOS. Calculate the rise time, fall time and the oscillation frequency of the oscillator. (only schematic is required)

Lab 8:

Out approximately on Monday, Nov. 7 Due on Monday, Nov. 14 (our next lab)

Power consumption: In this lab, we will measure the power consumption in an inverter. Create an inverter schematic with NMOS width = 5um and PMOS width = 15um. The load capacitance connected to the inverter should be 70fF. The input signal should be a pulse with rise time = fall time = 2n, pulse width =1n. In the ADE window, make sure Outputs > Save All > power (all) option is selected. Simulate the circuit for 14n. For help using the waveform calculator, please refer to the Waveform Calculator Tutorial.

a. Measure the average power of the gate;

b. Change the size of transistors: NMOS width = 10um and PMOS width = 30um. Measure the average power consumption.