Awarded:

1.  CMOS Foveal Image Senwor Chip
     Patent Number: 6,455,831
     Issue Date: Sep. 24, 2002
     Inventors:  Bandera; Cesar, Scott; Peter, Sridhar; Ramalingam, Xia; Shu
    Assignee:  Research Foundation of State University of New York, Albany, NY  

2. Method and apparatus for designing circuits for wave pipelining
   Patent Number:   5,796,624  (Divisional from 5,528,177)
   Issue Date:   Aug. 18, 1998
   Inventors:   Sridhar; Ramalingam, Xuguang; Zhang
   Assignee:  Research Foundation of State University of New York, Albany, NY

3. Logic Circuits for Wave Pipelining
    Patent Number: 5,701,094  (Divisional from 5,528,177)
    Issue Date:   Dec. 23, 1997
   Inventor(s): Sridhar; Ramalingam, Xuguang; Zhang
   Assignee:  Research Foundation of State University of New York, Albany, NY

4. Method and apparatus for selective clocking using a Muller-C element
   Patent Number:  5,646,554
   Issue Date:  07-08-1997
   Inventor(s):  Kim,  Seokjin and Sridhar, Ramalingam
   Assignee:  Research Foundation of State University of New York, Albany, NY

5.  Global threshold method and apparatus
 Patent Number:  5,621,815
 Issue Date: 04-15-1997
 Inventor(s): Talukdar; Dipankar, Sridhar; Ramalingam, Demjanenko; Victor
 Assignee(s): The Research Foundation of State University of New York, Buffalo, NY

6. Complementary field-effect transistor logic circuits for wave pipelining
 Patent Number:  5,528,177
 Issue Date:   06-18-1996
 Inventor(s):  Sridhar; Ramalingam, Xuguang; Zhang
 Assignee:  Research Foundation of State University of New York, Albany, NY

7. Single layer neural network circuit for performing linearly separable and non-linearly separable logical
operations
Patent Number: 5,535,309  (continuation of 05344436)
Issue Date: 07-09-1996
Inventors:   Shin; Yong-Chul; Sridhar; Ramalingam

8. Local adaptive contrast enhancement
 Patent Number:  5,524,070
 Issue Date:  06-04-1996
 Inventor(s): Shin; Yong-Chul, Sridhar; Ramalingam, Srihari; Sargur N., Demjanenko; Victor

9. Single layer neural network circuit for performing linearly separable and non-linearly separable logical operations
 Patent Number: 5,355,436
 Issue Date: 10-11-1994
 Inventor(s):  Shin; Yong-Chul, Sridhar; Ramalingam
 Assignee(s):  The Research Foundation, State University of New York at Buffalo, Buffalo, NY

10.  Programmable analog synapse and neural networks incorporating same
 Patent Number: 5,336,937
 Issue Date: 08-09-1994
 Inventor(s):  Sridhar; Ramalingam, Kim; Seokjin, Shin; Yong-Chul, Bogineni; Naidu C. R.
 Assignee(s): State University of New York, Buffalo, NY

11.  Digital data memory unit and memory unit array
 Patent Number: 5,257,220
 Issue Date: 10-26-1993
 Inventor(s): Shin; Yong-Chul,  Sridhar; Ramalingam,  Demjanenko; Victor, Palumbo; Paul W., Srihari; Sargur N.
Assignee(s): Research Foundation of the State Univ. of N.Y., Buffalo, NY