High Performance VLSI Systems and Architecture Laboratory

Department of Computer Science and Engineering

 

Director: Ramalingam Sridhar   Office: 338K Davis Hall, Lab location: 340 Davis Hall

Research Focus: VLSI Circuits and Systems, Embedded Technologies, Wireless Networks and Security, Computer Architecture

 

rsridhar_research_slide

 

Members  

Funding Source

Publications   

Patents 

 Research Group

Current Members

Ph.D. Graduates 

M.S. Graduates (Thesis)  

Other researchers

 

Current Students:

 

·         Kerry D. Courtright, Ph.D. candidate, "Tamper resistance and IP protection in embedded applications"

·         Sriram Sankaran, “Energy efficient security approach to sensor networks”

·         Mohammad Iftekhar Husain, “Cyber security and Computer Forensics”

·         Na Gong, “Very deep submicron VLSI Circuits and Systems”

 

Ph.D. Graduates:

 

Ashok Narasimhan, Ph.D. September 2009, Dissertation: “Variability and Power Aware Clock Network Design in Nanometer Technologies”

 

Geethapriya Thamilarasu, Ph.D. September 2009, Dissertation: “Cross-Layer Designs for Security in Wireless Ad Hoc Networks “, Assistant Professor, SUNY Institute of Technology, Utica, NY

 

Lushan Liu, Ph.D. May 2009, Dissertation: “Power aware Memory System Design for Very Deep Submicron (VDSM) SoCs”, Marvell Semiconductor, Santa Clara, CA

 

Praveen Elakkumanan, Ph.D. September 2006, Dissertation: “Overcoming the Circuit Design Challenges in Nanoscale SRAMs”; MS Thesis “Low Leakage High Performance Static Random Access Memories”, Aug 2003– IBM Semiconductor Research and Development Center, NY

 

Kris Schindler, Ph.D.February 2002, Thesis: "Energy Efficient Design Methodology for Combinational Logic Circuits" - University at Buffalo, CSE Department


Alfonso Martinez-Smith, Ph.D.  2000, Dissertation: "Framework and Methodology for Object-Based Hybrid Visual Processor Architecture Design" - Mutimedia Research Lab, Motorola CorporationSchaumbug, IL

 

Wen-Jann Yang , Ph.D., SUNY at Buffalo, September 1998, Dissertation: "Access Schemes for Multi-Attribute-Cecord Ctructure and Color-content based Image Retrieval" - Telecom Technology Services, Pleasonton, CA

 

Dipankar Talukdar, M.S. SUNY at Buffalo, 1993 Thesis: "An Adaptive Thresholding Technique and its ASIC implementation"; Ph.D. SUNY at Buffalo, June 1997, Dissertation: "Issues in the Design of Pipelined VLSI Circuits for DSP Applications" – Tzero Technologies, Sunnyvale, CA

 

Sanu MathewM.S. September 1997, Thesis: "Efficient Clocking of Wave-Domino Pipelined Systems"; Ph.D. September 1999, Dissertation: "Data-driven Self-timed logic systems" - Intel Microprocessor research lab,  Hillsboro, OR

 

Seokjin KimM.S. 1993. Ph.D. 1997, Dissertation: "Hierarchical Synchronization Scheme for Structured VLSI Systems, AMD, Boston, MA

 

Yong-Chul Shin, M.S. 1990, Thesis: "A General Purpose Parsing Processor for LALR Class of Languages";  Ph.D. 1994, Dissertation: "Non-Fully Configured Second-Order Neural Networks using Multi-Dimensional Weights" - CTO, Cedar Tech, Williamsville, NY


MS Graduates (Thesis)

 

Yawar M. Nahvi, M.S. February 2007, “Transmission-Gate based Variation Tolerant Active Clock Deskewing for Deep Submicron System on Chips (SoCs)”

 

Manjari Agarwal, M.S. August 2006, Thesis: “Charge-Sharing and Leakage Reduction in Domino CMOS Circuits”, - Continuing Ph.D.

 

Karthik Ramakrishnan, M.S. August 2006, Thesis: “Wireless Network Security using a Low cost Pseudo Random Number Generator”, - Morgan Stanley, New York, NY

 

Kishan Prasad, M.S. August 2005, Thesis: “Circuit Level Techniques for Reducing Radiation Induced Soft Error Rate (SER) in Nanoscale Combinational Circuits”

 

Aruna Balasubramanian, M.S. February 2005, “A Hybrid Security Solution for Mobile Ad Hoc Networks”, University of Massachusetts, Amherst, MA

 

Ghuru Kumaravelu, M.S. February 2005, “Virtual Cut ThroughSwitching for Network on Chip Architectures”. Pactron/HJPC, Sunnyvale, CA

 

Vijaykumar Vankadara, M.S. September 2004, “Cache Hierarchy Design for Memory Intensive Applications”, Canto, San Francisco, CA

 

Camil Fayad, M.S. February 2004, Thesis: “Montgomery Modular Arithmetic  Implementation in Crypto Engines for System on Chip (SOC) Design” - IBM Corporation, Poughkeepsie, NY

 

Roopa Raghunathan, M.S. September 2003, Thesis: "Power Reduction through Effective Slack Timing Utilization" – Magma Design Automation, Santa Clara, California

 

Ranjani Sridharan , M.S. September 2003, Thesis: "Reconfigurable Opcodes Instruction Set Architecture for Software Security" - Ph.D. at Texas A&M, College Station, TX


Srivathsan Krishnamohan, M.S. September 2003, Thesis: "Orthoganal Instruction Set Architecture for Network Capable Applicaiton Processor" - Ph.D. student Michigan State University, East Lansing, MI

 

Divya Chandrasekharan, M.S. September 2003, Thesis: "Accurate Power Estimation at Register Transfer Level with Leakage Consideration", - Mediatech, Virginia

Hanseu Park, M. .S. 2001, Thesis: "Impact of Deep Sub Micron on Technology on Wave-pipelining” - IBM Corporation


Veena Pureswaran,
M. .S. 2001, Thesis: "Reconfigurable DSP template for Multimedia processors” - IBM Corporation, North Carolina

 

Anand Lakshmanan, M.S. May 2001, Thesis: "Noise tolerant dynamic circuit” - Intel Corporation

 

Subramanian Sankaran, M.S. February 2000, Thesis: "Crosstalk analysis and clustered voltage scaling techniques in CMOS Designs" – Qualcomm, San Diego

 

Venkatesh Doraiswamy, M.S. February 2000, Thesis: "Impact of Interconnects on Deep submicron Wave-Pipeline designs" - Intel Corporation, Santa Clara, CA

 

Shu Xia, M.S.- “Foveal Vision System Design and characterization”, February 1999. Teradyne Corporation, Boston, MA

 

Shahar Dor, M.S. February 1998, Thesis: "On-line Delay-Fault Detection and Correction of Reliable Wave-Pipelining"Sun Microsystems - Austin, Texas

 

Jay AndersonM.S. August 1998, Thesis: "A New Circuit State Retention Scheme for Multi-threshold Voltage CMOS Circuits" - Ph.D. Carnegie Mellon University, Pittsburgh, PA


Hemil B. Patel,
M.S. September 1998, Thesis: "Supply-Threshold Voltage Scaling for Speed-Power Trade-Off" - LSI Logic


Daniel R. Pilhorn
M.S. September 1998, Thesis: "Issues in the Power Analysis of Digital Signal Processors" - Lockheed Martin Federal Systems Division

 

Paul DeMarco, M.S. September 1998, Thesis: "Issues in the Design of a DSP FPGA Architecture" - Lockheed Martin Federal Systems Division

 

Guhan Krishnan, M.S. September 1998, Thesis: "Partial Binding specifications for low power High Level Synthesis" – AMD, Boston, MA

 

Rajesh S. Parthasarathy, M.S. August 1997, Thesis: "Design of Wave pipelined Arithmetic Units using Double Pass Transistor Logic" - Intel Corporation, Hillsboro, Oregon

 

Mathew Greenberg, M.S., August 1997, Thesis: "A Hardware Implementation of a Two Dimensional Discrete Cosine Transform" - Applied Signal Technology, Sunnyvale, California

 

Brian McGee,  M.S. 1995, Thesis: "Low Power Issues in Wave Pipelined Systems" -Sun Microsystems, California

 

Enrique Fernadez Herrera, M.S. 1995, "Dual Rail Static CMOS Architecture for Wave Pipelining" - Universidad Centroamericana Jose Simeon Canas, El Salvador

 

Ramkumar Krishnamurthy, M.S. 1994, Thesis: "Wave-pipelined CMOS Implementation of Morphological Processors"; Ph.D. Carnegie Mellon University, Pittsburgh, PA.-  Intel Microprocessor Research Lab

 

Xuguang Zhang, M.S. 1994 - PairGain Technologies Inc., Tustin, California

 

Frank K. Li, M.S. 1993, Thesis: "Practical Asynchronous Design Techniques and Analysis"

 

Sanjay Fotedar, M.S. 1993. Thesis: "Underline Detection and Removal System using Hough Transform" - NCR Corporation


Chandra S. Bharathi,
M.S. 1993, Thesis: "Data Structures and Compression Techniques for a Large Read-only Memory resident database", - Intersolv.

 

Parag Gokhale, M.S. 1992. Thesis: "System Controller and System Integration for the Real-time Address Block Location System" - Accurate Corporation, New Jersey.


Douglas Hall,
M.S. 1992. Thesis: "A Processor for Symbolic and Numeric Applications.

 

Rajesh Dixit, M.S. 1992, Thesis: "Handwriting/Machine Print Discrimination and Character Recognition in Address Block Location System" - Jones Inc, Texas.

 

Sudeep Narain, M.S. 1991, Thesis: "Design and Simulation of an Architectural Framework for an Intelligent Decision Support System".


Dirk Naumann,
M.S. 1991, Thesis: "Design and Implementation of a Self-timed Microprocessor"

 

Vassilios Axaris, M.S. 1990, Thesis: "An Architecture for a Prolog Coprocessor". Emporiki Bank - Cyprus Ltd, Information Technology and Operations Division, Cyprus

 

Martin Gilbert, M.S. 1990.  Thesis: "Design Techniques for the realization of an Asynchronous RISC and Microcontroller - NASA Jet Propulsion Laboratory

 

Other Researchers

 

 Hua-Feng Chen, M.S. 1995, Broadcom, Arizona

 

Vidya Bharrgavi Balasubramanyn, MS (Project) 2007; Topic: Biosensor networks security


Srikanth Sundaram,
M.S. 2006. Research Topic: Sense Amplifiers – Texas Instruments, Texas

 

Charan Thondapu, M.S. 2005. Research Topic: SRAM Leakage control – Broadcom, California

Karthik Srinivasan, M.S. 2005. Research Topic: SRAM Leakage control – Apache Design Solutions, Mountain View, California

Bhooma Srinivasaraghavan, M.S. 2006. Research Topic: Drivers for Interconnects

 

Manish Kasotiya, M.S. 2005 Research Topic: Signaling for On-chip interconnects

 

Shantanu Divekar, M.S. 2005, Research Topic: Low power Clock distribution through current mode signaling

 

Viswanathan Natarajan, Research Topic: Security in RFID based Wireless networks

 

Viswanathan Ananthakrishnan. M.S. 2004, Research Topic: Soft Error and Leakage Control

 

Brian Bart, M.Eng. 1996. Project Title: “Foveal Vision sensor prototype design” - Intel Corporation, Folsom, California

Funding:

Microelectronic Design Center (MDC) supported by NYSTAR

National Science Foundation

NASA, Air Force, Amherst Systems.

Publications

2009

Kerry Courtright, Mohammad Iftekhar Husain, Ramalingam Sridhar, “LASE: Latency Aware Simple Encryption for Embedded Systems Security”, IJCSNS International Journal of Computer Science and Network Security, VOL.9 No.10, October 2009, pp. 1-6

M. I. Husain and R. Sridhar, “Towards a DDoS Resistant Network Architecture using Social Network Analysis”, ISCA 22nd International Conference on Computer Applications in Industry and Engineering (CAINE-2009), San Francisco, November 4 - 6, 2009

M. I. Husain and R. Sridhar, “iForensics: Forensic Analysis of Instant Messaging on Smart Phones”, The International Conference on Digital Forensics and Cyber Crime (ICDF2C), Albany, NY, October 2009

A. Narasimhan and R. Sridhar, “Variation aware Low Power Buffered Interconnect Design”, IEEE International System on Chip Conference (SoCC) 2009, Belfast, Ireland, September 9-11, 2009

G. Thamilarasu and R. Sridhar, "CIDS: Cross-layer Intrusion Detection System for Mobile Ad hoc Networks", International Journal of Mobile Network Design and Innovation (IJMNDI), 2009

G. Thamilarasu and R. Sridhar , "Game Theoretic Modeling of Jamming Attacks in Ad hoc Networks", International Conference on Computer Communications and Networks, ICCCN 2009, San Francisco, August 2009

A. Narasimhan and R. Sridhar, “Low Power Robust Clock Tree Buffer Insertion”, 3rd IEEE International Workshop on Design for Manufacturability & Yield, San Francisco, California, July 2009

S. Sankaran, M. I. Husain and R. Sridhar, “IDKEYMAN: An Identity-Based Key Management Scheme for Wireless Ad Hoc Body Area Network”, 4th Annual Symposium on Information Assurance, 12th Annual 2009 NYS Cyber Security Conference, Albany, NY, June 2009

G.Thamilarasu, R. Sridhar, "XLSEC - A Distributed Cross-layer Framework for Security in Wireless Sensor Networks", IEEE Consumer Communications and Networking Conference, (CCNC) Las Vegas, January 2009

2008

G. Thamilarasu, R. Sridhar, “Intrusion Detection in RFID Systems”, IEEE Military Communications Conference, 2008, San Diego, November 2008(Invited paper)

A. Narasimhan and R. Sridhar, “Variation Aware Low Power Buffered Interconnect Design”, Workshop on Design for Reliability and Verifiability, Oct 30-31, Santa Clara, CA

A. Narasimhan and R. Sridhar, “A Low Power and Low Area Active Clock Deskewing technique for Sub-90nm Technologies”, SoCC 2008, Page(s): 179-182

L. Liu, P. Nagaraj, S. Upadhyaya and R. Sridhar, “Defect Analysis and Defect Tolerant Design of Multi-port SRAMs”, Journal of Electronic Testing, Springer, Volume 24, Numbers 1-3 / June, 2008 165-179

2007

G. Thamilarasu and R. Sridhar, “Exploring Cross-layer Techniques for Security Challenges and Opportunities in Wireless Networks”, Invited paper, MILCOM 2007, Orlando, FL, October 2007

M. Agarwal, L. Liu, P. Elakkumanan and R. Sridhar, “Intra-Die Process Parameter Variation and Leakage Analysis of Cache at the Microarchitectural Level”, IEEE SoCC (System on Chip Conference), Hsinchu, Taiwan, September 2007

V. Ramaswamy, M. Agarwal and R. Sridhar, “A Robust 3GHz, CMOS Low Noise Amplifier for RFID Receivers”, IEEE SoCC (System on Chip Conference), Hsinchu, Taiwan, September 2007

L Liu, M. Agarwal, P. Elakkumanan and R. Sridhar, “CacheLeakage: A Leakage Aware Cache Simulator”, 50th Midwest Symposium on Circuits and Systems, Montreal, Canada, August 2007

G. Thamilarasu and R. Sridhar, “Toward Building a Multi-level Robust Intrusion Detection Architecture for Distributed Mobile Networks”, Fifth Inernational Workshop on Mobile Distributed Computing (MDC 07) in conjunction with International Conference on Distributed Computing Systems (ICDCS), Toronto, June 29, 2007

V. Bharrgavi Balasubramanyn, G. Thamilarasu and R. Sridhar, “Security Solution For Data Integrity In Wireless BioSensor Networks”, First International Workshop on Specialized Ad Hoc Networks and Systems (SAHNS 2007) in conjunction with International Conference on Distributed Computing Systems (ICDCS), Toronto, June 29, 2007

A. Narasimhan and R. Sridhar, “Impact of Variability on Clock Skew in H-tree Clock Networks”, International Symposium on Quality Electronic Design (ISQED), March 26-28, 2007, San Jose, CA

L Liu, M. Agarwal, P. Elakkumanan and R. Sridhar, “CacheSim: A Cache Memory Simulator with Intra-Die Process Parameter Variation and Leakage Models”, Austin Conference on Energy-Efficient Design (ACEED), 2007

A. Narasimhan, Y. Nahvi and R. Sridhar, “Variability Tolerant Reliable Clock Distribution Networks”, Austin Conference on Energy-Efficient Design (ACEED), 2007

2006

G. Thamilarasu, S. Mishra and R. Sridhar, “A Cross-layer approach to detect Jamming attacks in wireless ad hoc networks”, Invited paper, MilCom 2006, Washington, D.C., October 2006.

L. Liu, R. Sridhar and S. Upadhyaya, “A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells”, Defect and Fault Tolerance in VLSI Systems Symposium 2006, Washington, D.C., October 4-6, 2006.

M. Agarwal, P. Elakkumanan and R. Sridhar, “Leakage Reduction for Domino Circuits in sub-65nm Technologies”, IEEE System on Chip Conference (SoCC 06), Austin, TX, September 2006

P. Sharma, A. Khan, A. Narasimhan, S. K. Tripathi, R. Sridhar, “Energy Conservation in Sensor Networks through Selective Activation of Nodes using Thresholding”, IEEE International Symposium on a World of Wireless, Mobile and Multimedia Networks (WoWMoM) June 2006

S. Sundaram, P. Elakkumanan and R. Sridhar, “LPCSA: A Novel Low Power Current Sense Amplifier for Nanoscale SRAMs”, Austin Conference on Integrated Systems & Circuits, Austin, TX, May 17-19, 2006

P. Elakkumanan, K. Prasad, and R. Sridhar, “Improving Reliability of Nanoscale Designs by Concurrent Detection of Soft Errors”, Austin Conference on Integrated Systems & Circuits, Austin, TX, May 17-19, 2006

P. Elakkumanan, J. B. Kuang, K. Nowka, R. Sridhar, R. Kanj and S. Nassif, “SRAM Local Bit Line Access Failure Analysis”, International Symposium on Quality Electronic Design (ISQED), March 27-29, 2006, San Jose, CA, pp. 204-209.

P. Elakkumanan, K. Prasad, and R. Sridhar, “Time Redundancy Based Scan Flip-Flop Reuse to Reduce SER of Combinational Logic”, International Symposium on Quality Electronic Design (ISQED), March 27-29, 2006, San Jose, CA, pp. 617-624.

S. Sundaram, P. Elakkumanan and R. Sridhar, “High Speed Robust Current Sense Amplifier for Nanoscale Memories -- A Winner Take All approach”, 19th International Conference on VLSI Design, January 2006, pp. 569-574.

A. Narasimhan, B. Srinivasaraghavan  and R. Sridhar, “A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects”, 19th International Conference on VLSI Design, January 2006, pp.491-494.

2005

G. Thamilarasu, A. Balasubramanian, S. Mishra and R. Sridhar, "A Cross-Layer based Intrusion Detection System for Wireless Ad Hoc Networks", IEEE International Conference on Mobile Adhoc and Sensor Systems Conference - Workshop on Wireless Networks and Security (WSNS’05), Washington, DC, November 2005, pp. 855-861. 

V. Natarajan, A. Balasubramanian, S. Mishra and R. Sridhar, “Security for Energy Constrained RFID System”, AutoID2005, Fourth IEEE Workshop on Automatic Identification Advanced Technologies (AutoID’05), Buffalo, NY, October 17-18, 2005, pp. 181-186.

P. Elakkumanan, K. Prasad, and R. Sridhar, “Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits”, Journal of Low Power Electronics, American Scientific Publishers, August 2005, vol. 1, No. 2, pp. 182-193.

Karthik Ramakrishnan, A. Balasubramanian, S. Mishra and R. Sridhar, “Wireless Security Protocol using a Low Cost Pseudo Random Number Generator”, Milcom 2005, Atlantic City, NJ, October 17-20, 2005

A. Narasimhan, K. Srinivasan and R. Sridhar, “A High-Performance Router Design for VDSM NoCs”, IEEE System on Chip Conference, Washington, D.C., September 25-28, 2005, pp. 301-304

P. Elakkumanan, C. Thondapu and R. Sridhar, “DG-SRAM: A Low Leakage Memory Circuit”, IEEE System on Chip Conference, Washington, D.C., September 25-28, 2005, pp. 167-170

P. Elakkumanan, L. Liu, V. Vankadara and R. Sridhar, “CHIDDAM: A Data Mining based Technique for Overcoming the Memory Bottleneck Problem in Commercial Applications”, 48th IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, OH, August 7-10, 2005, pp. 1888-1891

A. Narasimhan, G. Kumaravelu, R. Sridhar, “An Investigation of the Impact of Network Parameters on Performance of Network-on-Chips”, 48th IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, OH, August 7-10, 2005, pp. 1617-1620

P. Elakkumanan, K. Thyagarajan, K. Prasad and R. Sridhar, “Optimal Vth Assignment and Buffer Insertion for Simultaneous Leakage and Glitch Minimization through Integer Linear Programming (ILP)”, 48th IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, OH, August 7-10, 2005, pp. 1880-1883

G. Thamilarasu, A. Balasubramanian, S. Mishra and R. Sridhar, “A Cross-Layer Approach to  Detecting DoS Attacks in Wireless Ad-Hoc Networks”, MobiHoc 2005, Sixth ACM International Symposium on Mobile Ad Hoc Networking and Computing, Urbana-Champaign, IL, May 25-28, 2005

V. Natarajan, A. Balasubramanian, S. Mishra and R. Sridhar, “Towards Providing Security for RFID Tags with Depleting Internal Energy”, MobiHoc 2005, Sixth ACM International Symposium on Mobile Ad Hoc Networking and Computing, Urbana-Champaign, IL, May 25-28, 2005

P. Elakkumanan, C. Thondapu, R. Sridhar, “RG-SRAM: A Low Gate Leakage Memory Design for Sub-70nm Process”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), May 11-12, 2005, Tampa, FL, pp. 295-296

A. Balasubramanian, S. Mishra and R. Sridhar, “Secure Key Management for NASA Communication”, 5th Integrated CNS Conference and Workshop, Fairfax, VA, May 3-5, 2005

A. Balasubramanian, S. Mishra and R. Sridhar, “Analysis of a Hybrid Key Management Solution for Ad Hoc Networks”, 2005 Wireless Communications and Networking Conference, New Orleans, March 13-17, 2005, vol. 4, pp. 2082-2087

P. Elakkumanan, C. Thondapu, R. Sridhar, “SRAM Designs to Reduce Gate and Sub-threshold Leakage Power in the Nanometer Domain”, Austin Conference on Energy Efficient Design (ACEED), 2005 (Best Poster Award)

P. Elakkumanan, S. Sundaram, R. Sridhar, “Process Variation Tolerant Low Power and High Speed Sense Amplifier Techniques for VDSM Caches”, Austin Conference on Energy Efficient Design (ACEED), 2005

A. Narasimhan, M. Kasotiya and R. Sridhar, “A Low-swing Differential Signaling Scheme for On-Chip Interconnects”, Proceedings, 18th International Conference on VLSI Design, 2005, pp. 634-639

A. Narasimhan, S. Divekar, P. Elakkumanan and R. Sridhar, "A Low-power Current-mode Clock Distribution Scheme for Multi-GHz NoC-based SoCs", Proceedings, 18th International Conference on VLSI Design, 2005, 130-133

2004

G. Tamilarasu, S. Mishra and R. Sridhar, “An Analysis of Cross-Layer Design Approach for Energy Conservation in Wireless Ad-Hoc Networks”,  1st IEEE Upstate NY Workshop on Communications and Networking, November 2004

P. Elakkumanan, S. Mishra and R. Sridhar, “A Novel Load Balanced Clustering Algorithm for Wireless Ad Hoc Networks with UAVs”,  1st IEEE Upstate NY Workshop on Communications and Networking, November 2004

A. Balasubramanian, S. Mishra and R. Sridhar, “An Enhanced Security Solution for Wireless Networks using Tradeoff Analysis”,  1st IEEE Upstate NY Workshop on Communications and Networking, November 2004

P. Elakkumanan, K. Thyagarajan, S. Mishra and R. Sridhar, “Dynamic MEXCLP based Balanced Clustering Algorithm for a Wireless Ad Hoc Network”, INFORMS 2004

R. Sridhar, "Clocking and Synchronization Issues in sub-100nm System on Chip (SoC) Designs", Invited Keynote, Dallas Circuits and Systems Workshop, September 2004

P. Elakkumanan, C. Thondapu and R. Sridhar, "A Gate Leakage Reduction Strategy for sub-70nm Memory Circuits”, Dallas Circuits and Systems Workshop, September 2004,  pp. 145-149

P Elakkumanan, V. Anathakrishnan, A Narasimhan and R Sridhar, "Leakage Aware SER Reduction Technique for UDSM Logic Circuits", Proceedings, IEEE International SoC Conference 2004, September 2004, pp. 82-85

A. Balasubramanian, S. Mishra and R. Sridhar. “A Hybrid Approach to Key Management for Enhanced Security in Ad Hoc Network”, University at Buffalo CSE Department, Technical Report, 2004-09, July 30, 2004

G. Tamilarasu, S. Mishra and R. Sridhar, "Cross Layer Approach to Low Energy Wireless Ad Hoc Networks ", NATO Cross Layer Workshop, NRL, Washington, D.C., June 2004

R Sridhar: System-on-Chip (SoC): Clocking and Synchronization Issues. VLSI Design 2004: 520-527

2003

P. Elakkumanan, A. Narasimhan and R. Sridhar, "NC-SRAM - A Low-Leakage Memory Circuit for Ultra-Deep Submicron Designs", Proceedings, IEEE International SoC Conference 2003, Portland, OR, September 2003, pp. 3-6

Ranjani Sridharan, Ramalingam Sridhar and Sumita Mishra, “A Robust Header Compression Technique for Wireless Ad Hoc Networks”, MobiHoc 2003. (also as) ACM SIGMOBILE Mobile Computing and Communication Review, vol. 7 Issue 3, pp. 23-24

2001

A. Lakshmanan and R. Sridhar, "Input Controlled Refresh for Noise Tolerant Dynamic Circuits," in Proc. Intl. Conf. ASIC/SOC, 2001, pp. 129--133

2000

A Martinez-Smith, J Wang, R Sridhar, and R Acharya, "Efficient Shape and Color Based Methods and Architecture for Content-Based Visual Retrieval",  Invited paper: Special Session: Image, Video, Audio Content Analysis and Indexing/Retrieval, First International Workshop on Intelligent Multimedia Computing and Networking (IMMCM'2000), Atlantic City, February 27-March 3, 2000

K. Schindler and R. Sridhar, "An efficient method for estimating switching activity in arithmetic circuits using a lumped delay model", ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International , 13-16 Sept. 2000, pp.119 - 123

1999

S. Mathew and R. Sridhar, "A data-driven micropipeline structure using DSDCVSL", Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 , 16-19 May 1999, Pages:295 - 298

1998

S. Xia, R. Sridhar, P. Scott and C. Bandera, "An All CMOS Foveal Image Sensor Chip", 11th IEEE International ASIC Conference, Rochester, NY, September 1998, 409-413

A. Martinez-Smith, S.K.Mathew and R. Sridhar, "System issues in the design of a Content-based Visual Coder", World Automation, Conference, May 1998, Anchorage, Alaska

S. Mathew and R. Sridhar, "Data-driven self-timed differential cascode voltage switch logic", ISCAS '98,  Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998. Volume: 2, 31 May-3 June 1998 Pages:165 - 168 vol. 2

R. S. Parthasarathy and R. Sridhar, "Double Pass Transistor Logic for High Performance Wave Pipeline Circuits", 11th International Conference on VLSI Design, January 1998, Chennai, India, pp. 495-500

1997

R. Sridhar ,and K. Schindler, "Instruction level power metric and its application to low power DSP system", Asilomar Conference on Circuits and Systems, Special session on low power systems, November 1997, 119-123

 A. Martinez-Smith, S. K. Mathew and R. Sridhar,   "Design and Implementation of and Object-Based Video Coder Chip Set based on Syntactic Pattern Recognition", IEEE International ASIC Conference, September 1997, Portland, Oregon

I. J. Osele and R. Sridhar, "Probability based delay analysis and tuning of VLSI Circuits using a variance-covariance method", PATMOS `97, France, September 1997

W. Yang, R. Sridhar and P. Palumbo "Multi-attribute Lexicon Generation by Hyperlinked Embedded Access Structure,  IEEE 1997 International Database Engineering and Applications Symposium, Montreal. August 25-271997, pp. 299-306

S. Kim and R. Sridhar, "Buffered Single-Phase Clocked Logic for High-speed CMOS pipelined circuits", IEEE International Symposium on Circuits and Systems  `97, June 1997, Hong Kong

S. K. Mathew and R. Sridhar, "Efficient Clocking of a Wave Domino Pipeline", IEEE International Symposium on Circuits and Systems  `97, June 1997, Hong Kong

S. Kim and R. Sridhar, "Hierarchical Synchronization Scheme Using Self-timed Mesochronous Interconnections", IEEE International Symposium on Circuits and Systems  `97, June 1997, Hong Kong

W. Yang, R. Sridhar and V. Demjanenko "Exploiting the Parallelism and Processing Schemes of Intersecting Compressed Bit Vectors for Inverted File Organization" International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'97), Las Vegas, June 1997

1996

S. Kim and R. Sridhar, "A Hardware Design Rule Checker Using a CAM Architecture'', Journal of VLSI Design, Special Issue on Hardware Accelerators for VLSI Design, September 1996.  vol. 4, No. 2, pp. 141-147

D. Talukdar and R. Sridhar, "An Analytical Approach to Fine Tuning in CMOS Wave-pipelining", IEEE International ASIC Conference, Sep. 1996, pages 205-208

A. Martinez-Smith and R. Sridhar, "On-line Detection of Environmentally Induced Delay Faults in CMOS Wave Pipelined Circuits", IEEE International ASIC Conference, Sep. 1996, pp. 57-60

R. Sridhar, A. Martinez-Smith and B. McGee, "Speed and power comparison of CMOS Wave-pipelined  Systems and Low power WTGL", ISCAS `96, Atlanta, GA

D. Talukdar and R. Sridhar, "DSP Circuit Structure and FPGA Architectural Requirements for a DSP FPGA",  Field Programmable Devices 96, May 13-14, 1996, Toronto, Canada

 

S. Kim and R. Sridhar, "Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems", Sixth Great Lakes Symposium on VLSI, March, 1996, Iowa

W. Yang, R. Sridhar, and V. Demjanenko, "Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses", Second International Symposium On High-Performance Computer Architecture (HPCA), February  4-7, 1996, San Jose, CA, pp. 232-241

G. Enrique Fernandez and R. Sridhar, "Dual Rail Static CMOS Architecture for Wave Pipelining", Proc. 9th IEEE International Conference on VLSI Design, January 1996, Bangalore, India, pp. 335-336

1995

R. Krishnamurthy and R. Sridhar, "A CMOS Wave-pipelined Image Processor for Real-time Morphology", in Proc. IEEE Intl. Conf. on Computer Design:  Austin, TX, 1995, 638-643

S. Kim and R. Sridhar, "A Local Clocking Approach for Self-timed Data Path Designs", 5th IEEE Great Lakes Symposium on VLSI, March 16-18, 1995, Buffalo, NY, 152-155

R. Sridhar, T. Jones, "VLSI in Biomedical Imaging Systems", Computerized Medical Imaging and Graphics, vol.19, no. 1, pp. 161-169, January 1995

Palumbo, S. N. Srihari, J. Soh, R. Sridhar and V. Demjanenko, "Postal Address Block Location in Real-Time", in Document Image Analysis, Ed, L O'Gorman and R. Kasturi, 1995 pp 382-390

1994

H. R. Rao, R. Sridhar and S. Narain, "An Active Intelligent Decision Support System - Architecture and Simulation", Decision Support Systems, December 1994, pp. 79-91

X. Zhang and R. Sridhar, "Synchronization of Wave-Pipelined Circuits'', in Proc. IEEE Intl. Conf. on Computer Design: VLSI in Computer and Processors, Cambridge, MA, 1994, pp. 164-167

X. Zhang and R. Sridhar, "CMOS Wave-Pipelining using Transmission Gate Logic'', Proceedings, Seventh IEEE ASIC Conference, Sept. 1994,  pp. 92-95

 S. Kim and R. Sridhar, "Comparison of Power Consumption among asynchronous design style with their synchronous counterparts", 37th Midwest Symposium on Circuits and Systems, Lafayette, LA, August 3-5, 1994, pp. 7-10, vol. 1

1993

M. Gilbert and R. Sridhar, "AMEC - An Asynchronous Microprogrammable Execution Controller'', Microprocessing and Microprogramming, The Euromicro Journal, 36, 1992-1993, pp. 9-25

 D. Talukdar and R. Sridhar, "Adaptive Thresholding ASIC for Image Processing Application"; IEEE International ASIC Conference; September 29, 1993; Riverside Convention Center, Rochester, New York, pp. 104-107

D. Talukdar and R.Sridhar "A Programmable Implementation of FIR Filters using Bernstein Polynomial"; 1993 IEEE Workshop on VLSI  in Communications, September 16, 1993, Stanford Sierra Camp, Lake Tahoe, California

 R. Sridhar and Yong-Chul Shin, "VLSI Neural Network Architectures", IEEE International ASIC Conference, 1993, Rochester, NY, September 1993, pp. 560-569

 D. Talukdar and R. Sridhar, ``Adaptive Thresholding ASIC for Imaging Applications'', IEEE International ASIC Conference, 1993, Rochester, NY, September 1993, pp. 104-107

 Y.-C. Shin and R. Sridhar, ``Network Configurations and Training Speeds of Second-Order Neural Networks'', World Congress on Neural Networks 1993, Portland, Oregon, July 1993, pp.I-585-588

S. J. Kim, Y. -C. Shin, N. C. R. Bogineni and Ramalingam  Sridhar, "A Programmable Analog CMOS Synapse for Neural Network", in Analog VLSI Neural Networks, edited by Y. Takefuji, 1993, Kluwer Academic Publishers, Boston, Massachusetts pp. 83-90

 S.J. Kim, Y.-C. Shin and R. Sridhar, ``An Analog Neural Network with Four-Quadrant Floating-Gate Synapse'', World Congress on Neural Networks 1993, Portland, Oregon, July 1993, I-547-550

 Y. C. Shin, R. Sridhar and S. N. Srihari, ``Contrast Enhancement based on Window statistics", SPIE/IST Symposium on Electronic Imaging Science and Technology, San Jose, California, February 1993, vl. 1906, pp. 37-48

1992

 J. J. Hull, V. Demjanenko, R. Sridhar and S. N. Srihari, ``Architectural Design for Address Interpretation in a Laboratory Address Recognition Unit (LARU)", Proceedings, USPS Advanced Technology Conference, Washington, D.C., December 1992, Volume 3, pp. 1313-1323

  Y. C. Shin and R. Sridhar, ``Artificial Neural Network with Complex Weight and Its Training", Proceedings, RNNS/IEEE Symposium on Neuroinformatics and Neurocomputing, Russia, October 1992, pp. 354-361

 R. Sridhar, ``A Tutorial on Asynchronous Design Techniques", Proceedings, Fifth Annual IEEE International ASIC Conference, Rochester, NY, IEEE Computer Society, September 1992, pp. 296-300

Y. C. Shin, R. Sridhar, V. Demjanenko, P. W. Palumbo and J. J. Hull, ``Image Processing ASIC for Real-time Contrast Enhancement", Proceedings, Fifth Annual IEEE International ASIC Conference, Rochester, NY, IEEE Computer Society, September 1992, pp. 197-200

V. Axaris and R. Sridhar, "A Prolog Co-processor with a Backtrack Management Unit", Intl Journal of Mini and Microcomputers, vol. 14, No. 3, 1992, pp. 153-160

 Kim, Y.-C. Shin, N. C. R. Bogineni and R. Sridhar, "A Programmable Analog CMOS Synapse for Neural Network", Journal Analog Integrated Circuits and Signal Processing (AICSP), 2, 345-352 (1992), Kluwer Academic Publishers, Boston, Massachusetts

Palumbo, S. N. Srihari, J. Soh, R. Sridhar and V. Demjanenko, "Postal Address Block Location in Real-Time", IEEE Computer, Special Issue on Document Image Analysis Systems, vol. 25, No. 7, July 1992,  pp. 34-42

Y. Shin, R. Sridhar, V. Demjanenko, P. W. Palumbo and S. N. Srihari, "A Special Purpose Content Addressable Memory Chip for Real-Time Image Processing", IEEE Journal of Solid-State Circuits, vol. 27, No. 5, May 1992,  pp. 737-744

 Y. C. Shin, R. Sridhar, V. Demjanenko, P. W. Palumbo and J. J. Hull, ``Contrast Enhancement of Mail Piece Images", SPIE/IST Symposium on Electronic Imaging Science and Technology, San Jose, California February 1992, Proceedings, Machine Vision Applications in Character Recognition and Industrial Inspection, SPIE Vol. 1661 pp. 27-37

1991

  Y. C. Shin, R. Sridhar, V. Demjanenko, P.W. Palumbo and S. N. Srihari, ``Special Purpose Register Array for Real-Time Image Processing", Proceedings, Fourth Annual IEEE International ASIC Conference, September 1991, Rochester, New York, pages P18-1.1 -- P18-1.4

1990

  P. W. Palumbo, J. Soh, S. N. Srihari, V. Demjanenko and R. Sridhar, ``Real-Time Address Block Location using Pipelining and Multiprocessing", Proceedings, USPS Fourth Advanced Technology Conference, Washington D.C., November 1990, Volume 1, pp. 73-87.

  V. Demjanenko, Y. C. Shin, R. Sridhar, P. W. Palumbo and S. N. Srihari,``Real-Time Connected Component Analysis for Address Block Location", Proceedings, USPS Fourth Advanced Technology Conference, Washington D.C., November 1990, Volume 3, pp. 1059-1071.

 V. Axaris and R. Sridhar, ``Backtracking Management Unit for Prolog Implementation", Proceedings of North American Conference on Logic Programming '90, Austin, Texas, November 1990.

 R. Sridhar, ``An Intelligent Decision Support System for VLSI Design", Proceedings of the Northcon 90, Feature Session on Combined Analog and Digital Integrated Circuits, IEEE, Seattle, October 1990.

 H. R. Rao, R. P. Cerveny, G. L. Sanders, R. Sridhar, and E. J. Garrity, ``Intelligent Control and Resolution of a Network of Learning and Problem Solving Processors", Proceedings of 23rd Annual Hawaiian International Conference on System Sciences, Volume 1V, Edited by Ralph H. Sprague, IEEE Computer Society, January 1990, pp. 316-325.

Before 1990

 R. Sridhar, H. R. Rao and S. Narain, ``A Multiprocessor Implementation of an Intelligent Decision Support System", Proceedings of ISMM Conference on Intelligent Distributed Processing, December 1989

 M. L. Manwaring, R. Sridhar and Y. P. Chiang, ``Direct Execution - A Language-Directed approach to Processor Design", International Society of Mini and Microcomputers Conference, Mini and Microcomputers - From Micros to Supercomputers, December 1988, ACTA Press, pp. 355-358

R. Sridhar and M. L. Manwaring, "An Automatic Microcode Generator for High Level Language Machines", Microprocessing and Microprogramming, The Euromicro Journal, December 1986, Vol. 18, Numbers 1-5, pp. 263-268

 M. L. Manwaring, J. L. Meador, R. Sridhar and T. Glagowski, ``On Obtaining Objective Performance Evaluations between High and Low Level Language Machines", Proceedings of the Eighteenth Asilomar Conference on Circuits, Systems and Computers, IEEE Computer Society, November 1984, pp. 358-362

 R. Sridhar and M. L. Manwaring, ``A Microcoded Direct Execution BASIC", Proceedings of the Seventeenth Asilomar Conference on Circuits, Systems and Computers, IEEE Computer Society, November 1983, pp. 71-74

 R. Sridhar and M. L. Manwaring, ``RISC, CISC and Direct Execution Architectures - An Analysis", International Society of Mini and Microcomputers Conference, December 1988
 

 PATENTS

Awarded:

1.  CMOS Foveal Image Senwor Chip
     Patent Number: 6,455,831
     Issue Date: Sep. 24, 2002
     Inventors:  Bandera; Cesar, Scott; Peter, Sridhar; Ramalingam, Xia; Shu
    Assignee:  Research Foundation of State University of New York, Albany, NY
 

2. Method and apparatus for designing circuits for wave pipelining
   Patent Number:   5,796,624  (Divisional from 5,528,177)
   Issue Date:   Aug. 18, 1998
   Inventors:   Sridhar; Ramalingam, Xuguang; Zhang
   Assignee:  Research Foundation of State University of New York, Albany, NY

3. Logic Circuits for Wave Pipelining
    Patent Number: 5,701,094  (Divisional from 5,528,177)
    Issue Date:   Dec. 23, 1997
   Inventor(s): Sridhar; Ramalingam, Xuguang; Zhang
   Assignee:  Research Foundation of State University of New York, Albany, NY

4. Method and apparatus for selective clocking using a Muller-C element
   Patent Number:  5,646,554
   Issue Date:  07-08-1997
   Inventor(s):  Kim,  Seokjin and Sridhar, Ramalingam
   Assignee:  Research Foundation of State University of New York, Albany, NY

5.  Global threshold method and apparatus
 Patent Number:  5,621,815
 Issue Date: 04-15-1997
 Inventor(s): Talukdar; Dipankar, Sridhar; Ramalingam, Demjanenko; Victor
 Assignee(s): The Research Foundation of State University of New York, Buffalo, NY

6. Complementary field-effect transistor logic circuits for wave pipelining
 Patent Number:  5,528,177
 Issue Date:   06-18-1996
 Inventor(s):  Sridhar; Ramalingam, Xuguang; Zhang
 Assignee:  Research Foundation of State University of New York, Albany, NY

7. Single layer neural network circuit for performing linearly separable and non-linearly separable logical
operations
Patent Number: 5,535,309  (continuation of 05344436)
Issue Date: 07-09-1996
Inventors:   Shin; Yong-Chul; Sridhar; Ramalingam

8. Local adaptive contrast enhancement
 Patent Number:  5,524,070
 Issue Date:  06-04-1996
 Inventor(s): Shin; Yong-Chul, Sridhar; Ramalingam, Srihari; Sargur N., Demjanenko; Victor

9. Single layer neural network circuit for performing linearly separable and non-linearly separable logical operations
 Patent Number: 5,355,436
 Issue Date: 10-11-1994
 Inventor(s):  Shin; Yong-Chul, Sridhar; Ramalingam
 Assignee(s):  The Research Foundation, State University of New York at Buffalo, Buffalo, NY

10.  Programmable analog synapse and neural networks incorporating same
 Patent Number: 5,336,937
 Issue Date: 08-09-1994
 Inventor(s):  Sridhar; Ramalingam, Kim; Seokjin, Shin; Yong-Chul, Bogineni; Naidu C. R.
 Assignee(s): State University of New York, Buffalo, NY

11.  Digital data memory unit and memory unit array
 Patent Number: 5,257,220
 Issue Date: 10-26-1993
 Inventor(s): Shin; Yong-Chul,  Sridhar; Ramalingam,  Demjanenko; Victor, Palumbo; Paul W., Srihari; Sargur N.
Assignee(s): Research Foundation of the State Univ. of N.Y., Buffalo, NY