module ex3_29b;
    /* gate level model to implement fig 3.29b */
    
   wire x,y,z;
   wire F;
   
   fig329 f1(F, x,y,z);
  fig329Test f1test (x,y,z, F);

endmodule



module fig329 (F, x, y, z);  
   output F;
   input x,y,z;
   wire  xp,yp,zp,t1,t2,t3;
   
 
   not g1 (xp,x);
   not g2 (yp,y);
   not g3 (zp,z);
   
   nand g4 (t1,xp,y);
   nand g5 (t2,x,yp);

   and g6 (t3,t1,t2);
   and g7 (F,t3,z);
      
endmodule


module fig329Test (x,y,z, F);
   input F;
   output x,y,z;
   reg [2:0] d;
   reg x,y,z;
   
    
   integer 	    i;
   
    initial begin       
     $monitor ("x: %b  y: %b z: %b  F: %b", x,y,z,F);
       
       for (i=0; i<8; i=i+1) 
         begin d = i; 
            x=d[2];
	    y=d[1];
	    z=d[0];
            #10000 ;end 
       $finish; 
    end 
endmodule