Course Description

Description and Syllabus and Tentative Schedule

Lecture Material

It is assumed that the following course material is being made available to students of SUNY at Buffalo for use in the courses offered by the Department of Computer Science.
They are meant for instructional use only.

Date	Topic	Reading material	Notes/comments
1/12	Introduction to CSE341: Policies and protocols	First day handout
1/16-21	Introduction to Computer Organization; Instruction set architecture	Intro-ISA
1/23	MIPS assembly and SPIM	Simple MIPS program	SPIM Docs
1/26	Logical and shift operations	LogicShift
1/28	Procedure call, stack and frame pointers, delayed branch	ProcSP	RegisterMap
2/2	Arithmetic algorithms	ArithAlg
2/4	Hardware description lanaguage	Verilog
2/6	Verilog continued	Verilog
2/9	Gate Level Design using Verilog	VerilogCh4	AdderModule
2/11	Multiplier	Mult
2/13	Floating point unit (adder, multipler)	FP
2/16	Floating point represention + FP adder Implementation	IEEE754&FPAdder
2/18	Lets design a data path for MIPS	Ch.5	Hwk5: basic datapath classowork
2/19	More details on datapath	DPControl
2/27	Midterm review	Review
3/2	Project discussion; complete datapath design
3/6	Midterm Exam
3/16	Pipelining	Ch.6 Intro PPLNG
3/18	Pipelined Datapath	PPLNG2
3/20	Pipelined datapath handling hazards	PPLNG3
3/22	Project (Take 2)	Newer Project Description
3/27	Pipelining (stalls and control hazards)	Hazz
3/30	Branch prediction	Br.Predict
4/1	Performance Evaluation	Perf	Project with more explanation
4/3	Performance: Exercises	PerfExercises	4.1, 4.2, 4.3, 4.6, 4.7, 4.8, 4.9, 4.10,4.11,4.12, 4.13, 4.17
4/8	Memory Hierachy (Cache)	Cache
4/13	Cache organization	CacheOrg
4/15	Cache-MainMemory	CacheMM
4/17	Final Exam review	FinalReview
4/19	Associative and Multi-level cache	L1L2Cache
4/22	Review Pipelined Datapath	PipelineExercises	1.2,6.3,6.4, 6.6,6.39
5/1	Please see the Final review we discussed in class	Final Review

Project Descriptions

Term project: Mini-MIPS DataPath Design   (Updated version Arpil 2)
Verilog tutorial

Homework:

Hoemwork#	Due date	Topic
Hwk1	1/30	MIPS and XSPIM
Hwk2	2/9	Procedure call
Hwk3 (new and improved)	2/20 (new date)	Verilog Exercises
Hwk4: 3.42, 3.44 Edition 3	2/27	Floating Point Rep
Hwk5	Done	Basic Datapath

Graduate Teaching Assistant: Raghuram Sudaakar (rs96@buffalo.edu)

Office hours:
10am -11am on Tue and
3.30 pm-4.30pm on Thu at Bell 329.