Course Description

Description 

Lecture Material

It is assumed that the following course material is being made available to students of SUNY at Buffalo for use in the courses offered by the Department of Computer Science.
They are meant for instructional use only.

Date	Topic	Reading material	Notes/comments
1/18	Introduction to CSE341: Policies and protocols	First day handout
1/20	Processor performance measurement	Perf	see hwk1 below
1/23	Instruction Set Architecture	ISA (chap 2)	Register Map
1/27	Working with an ISA	add.txt add1.txt
1/30	Thinking ISA	MoreISA
2/1	Selection, iteration, and procedure call; parameter passing; syscalls	selection  iteration procedure call
2/3	More iteration; Delayed branch, NOPs	ArrayAccess
2/6	Computer arithmetic algorithms: addition, multiplication; Very Preliminary Introduction to Verilog	Slowing moving on to Ch.3
2/10	Floating point arithmetic	Ch.3; FP
2/13	FP additon: example, algorithm, hardware	Ch.3	Hwk2,3 assigned
2/20	Introduction to Datapath design; from ISA to implementation	onto Ch.4
2/22	Introduction to Hardware Description Language: Verilog	Verilog	Adder.v
2/27	Continue verilog	Full modules; Delays and timing
2/29	Leap day: Review for midterm
	Verilog description with testbench	example
3/7	Midterm Exam	Note the date change
3/12-16	Spring Break
3/19	Review of Datapath Design (lab3); New topic: Pipelined execution	Synthesis using Verilog
3/26	Pipeline hazards: data, control, structural
3/28	Pipelined datapath
4/2	Data Forwarding; Branch Prediction;	Verilog synthesis: Mux4 +MuxTestbench, Mux32
4/9-4/16	Cache, Cache design: direct, set-associative	Ch.5
4/16	Multi-processor; multi-core	Ch.7	GPUComputing fovealchip
4/20	Final Review	review

Project Descriptions

MARS MIPS Simulator
MIPS Downlod and Tutorial Documentation
Verilog tutorial
More useful links for Verilog: tutorial1
Simulator

Homework:

Homework/lab	Due date	Topic
HWK#1	2/3	Evolution of Computer Architecture
Lab#1	2/20 (new date)	Thinking ISA (Note this is a lab: see details in the description)
HWK#2	2/27	1.1.3a, 1.3.2a, 1.3.3a, 1.4.1a, 1.5.4a
Hwk#3	3/2	1.15.1a, 2.6.4b, 2.7.1a, 2.7.2b, 2.7.3b
Lab#2	3/21	Define the FP Adder and FP Multipler of Ch.3 in Verilog; include a tester for each of the moudle; submit FPAdder.v FPMult.v
Lab#3	4/27	Design of a simple datapath

Graduate Teaching Assistant: 

Office hours:
Dingchen Ren:  3.00-5.00PM Mon; 1-2PM Tues
                         Outside/Inside Davis 301

Meng Liu: Wed 8.50-9.50AM, Thu: 3.30-5.30PM
                  Outside Davis 301

Recitations:

     Mon 9.00 - 9.50 AM  Capen 260

     Thu  3.00 - 3.50 PM Park 250

     Fri   11.00 - 11.50 AM Norton 210